元器件交易网www.cecb2b.comADS8402 SLAS1B – DECEMBER 2002 – REVISED MAY 200316-BIT, 1.25 MSPS, UNIPOLAR DIFFERENTIAL INPUT, MICRO POWER SAMPLINGANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCEFEATURESD1.25-MHz Sample RateD16-Bit NMC Ensured Over TemperatureDZero LatencyDUnipolar Differential Input Range: Vref to –VrefDOnboard ReferenceDOnboard Reference BufferDHigh-Speed Parallel InterfaceDPower Dissipation: 155 mW at 1.25 MHz TypDWide Digital SupplyD8-/16-Bit Bus TransferD48-Pin TQFP PackageAPPLICATIONSDDWDMDInstrumentationDHigh-Speed, High-Resolution, Zero LatencyDDDData Acquisition SystemsTransducer InterfaceMedical InstrumentsCommunicationDESCRIPTIONThe ADS8402 is a 16-bit, 1.25 MHz A/D converter with aninternal 4.096-V reference. The device includes a 16-bitcapacitor-based SAR A/D converter with inherent sampleand hold. The ADS8402 offers a full 16-bit interface and an8-bit option where data is read using two 8-bit read cycles.The ADS8402 has a unipolar differential input. It isavailable in a 48-lead TQFP package and is characterizedover the industrial –40°C to 85°C temperature range.SAR+IN–INREFIN+_OutputLatchesand3-StateDriversBYTE16-/8-BitParallel DATAOutput BusCDACComparatorRESETConversionandControl LogicCONVSTBUSYCSRDREFOUT4.096-VInternalReferenceClockPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstrumentssemiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date. Productsconform to specifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.Copyright 2002–2003, Texas Instruments Incorporated元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam duringstorage or handling to prevent electrostatic damage to the MOS gates.ORDERING INFORMATIONMAXIMUMINTEGRALLINEARITY(LSB)MAXIMUMDIFFERENTIALLINEARITY(LSB)NOMISSINGCODESRESOLU-TION (BIT)PACKAGETYPEPACKAGEDESIGNATORTEMPER-ATURERANGEORDERINGINFORMATIONTRANS-PORTMEDIAQUANTITYTape andreel 250Tape andreel 1000Tape andreel 250Tape andreel 1000MODELADS8402I±6–22~+3318 PinTQFPPFB–40°C to85°CADS8402IPFBTADS8402IPFBRADS8402IBPFBTADS8402IBPFBRADS8402IB±3.535–11~+2218 PinTQFPPFB–40°C to85°CNOTE:For the most current specifications and package information, refer to our website at www.ti.com.ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range unless otherwise noted(1)UNITVoltage+IN to AGND–IN to AGND+VA to AGNDVoltage rangeVoltage range+VBD to BDGND+VA to +VBDDigital input voltage to BDGNDDigital output voltage to BDGNDOperating free-air temperature range, TAStorage temperature range, TstgJunction temperature (TJ max)Power dissipationTQFPpackageTQFP packageθJA thermal impedanceVapor phase (60 sec)LeadtemperaturesolderingLead temperature, solderingInfrared (15 sec)+VA + 0.1 V+VA + 0.1 V–0.3 V to 7 V–0.3 V to 7 V–0.3 V to 2.5 V–0.3 V to +VBD + 0.3 V–0.3 V to +VBD + 0.3 V–40°C to 85°C–65°C to 150°C150°C(TJMax – TA)/θJA86°C/W215°C220°C(1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.2元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003SPECIFICATIONSTA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MHz (unless otherwise noted) PARAMETERTEST CONDITIONSMINTYPAnalog InputFull-scale input voltage (see Note 1)AbsoluteinputvoltageAbsolute input voltageCommon-mode input rangeInput capacitanceInput leakage currentSystem PerformanceResolutionNomissingcodesNo missing codesIntegrallinearity(seeNotes2and3)Integral linearity (see Notes 2 and 3)DifferentiallinearityDifferential linearityOffseterror(seeNote4)Offset error (see Note 4)Gainerror(seeNotes4and5)Gain error (see Notes 4 and 5)CommonmoderejectionratioCommon-mode rejection ratioNoiseDC Power supply rejection ratioSampling DynamicsConversion timeAcquisition timeThroughput rateAperture delayAperture jitterStep responseOvervoltage recovery(1)Ideal input span, does not include gain or offset error.(2)LSB means least significant bit(3)This is endpoint INL, not best fit(4)Measured relative to an ideal full-scale input (+IN – –IN) of 8.192 V(5)This specification does not include the internal reference voltage error and drift.2251001001501.25610nsnsMHznspsnsnsAt 7FFFh output code,+VA = 4.75 V to 5.25 V,Vref = 4.096 V, See Note 4ADS8402IADS8402IBADS8402IADS8402IBADS8402IADS8402IBADS8402IADS8402IBADS8402IADS8402IBAt dc (±0.2 V around Vref/2)+IN – –IN = 1 Vpp at 1 MHz1516–6–3.5–2–1–3–1.5–0.15–0.0988080601±2.5±2±1±0.75±1±0.563.53231.50.150.09816BitsBitsLSBLSBmVmV%FSdBµV RMSLSBADS8402I+IN – –IN+IN–IN–Vref–0.2–0.2(Vref/2) – 0.2Vref/2250.5VrefVref + 0.2Vref + 0.2(Vref/2) + 0.2VVVpFnAMAXUNIT3元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003SPECIFICATIONS (CONTINUED)TA = –40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MHz (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPDynamic CharacteristicsTotal harmonic distortion (THD) (see Note 1)Signal-to-noise ratio (SNR)Signal-to-noise + distortion (SINAD)Spurious free dynamic range (SFDR)–3dB Small signal bandwidthExternal Voltage Reference InputReference voltage at REFIN, VrefReference resistance (see Note 2)Internal Reference OutputInternal reference start-up timeVref rangeSource CurrentLine RegulationDriftDigital Input/OutputLogic familyVIHVILVOHVOLIIH = 5 µAIIL = 5 µAIOH = 2 TTL loadsIOL = 2 TTL loads+VBD–1–0.3+VBD – 0.602’sComplement+VBD (see Notes 3 and 4)+VA (see Note 4)fs = 1.25 MHzfs = 1.25 MHz2.9.753.35311555.255.2534VVmAmW°CCMOS+VBD + 0.30.8+VBD0.4VFrom 95% (+VA), with 1 µFstorage capacityIOUT = 0Static load+VA = 4.75 ~ 5.25 VIOUT = 00.63.06.0961204.1310msVµAmVPPM/C2..0965004.2VkΩVIN = 8 Vpp at 100 kHzVIN = 8 Vpp at 100 kHzVIN = 8 Vpp at 100 kHzVIN = 8 Vpp at 100 kHz–95 90855dBdBdBdBMHzMAXUNITLilLogic levellData formatPower Supply RequirementsPPower supply voltagellt+VA Supply current (see Note 5)Power dissipation (see Note 5)Temperature RangeOperating free-air–4085(1)Calculated on the first nine harmonics of the input frequency(2)Can vary ±20%(3)The difference between +VA and +VBD should not be less than 2.3 V, i.e., if +VA is 5.25 V, +VBD should be minimum of 2.95 V.(4)+VBD≥ +VA – 2.3 V(5)This includes only VA+ current. +VBD current is typically 1 mA with 5 pF load capacitance on output pins.4元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003TIMING CHARACTERISTICSAll specifications typical at –40°C to 85°C, +VA = +VBD = 5 V (see Notes 1, 2, and 3)PARAMETERtCONVtACQtpd1tpd2tw1tsu1tw2tw3tw4th1td1tsu2tw5tentd2td3tw6th2tpd4tsu3th3tdisConversion timeAcquisition timeCONVST low to conversion started (BUSY high)Propagation delay time, End of conversion to BUSY lowPulse duration, CONVST lowSetup time, CS low to CONVST lowPulse duration, CONVST highCONVST falling edge jitterPulse duration, BUSY signal lowPulse duration, BUSY signal highHold time, First data bus data transition (RD low, or CS low for read cycle, or BYTE inputchanges) after CONVST lowDelay time, CS low to RD lowSetup time, RD high to CS highPulse duration, RD low timeEnable time, RD low (or CS low for read cycle) to data validDelay time, data hold from RD highDelay time, BYTE rising edge or falling edge to data validRD highHold time, last RD (or CS for read cycle ) rising edge to CONVST falling edgePropagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edgeSetup time, BYTE rising edge to RD falling edgeHold time, BYTE falling edge to RD falling edgeDisable time, RD High (CS high for read cycle) to 3-stated data bus022050Max(td5)002002040005020Min(tACQ)63020020101503520MINTYP600MAX610UNITnsnsnsnsnsnsnspsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnstd5Delay time, BUSY low to MSB data valid(1)All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.(2)See timing diagrams.(3)All timings are measured with 20 pF equivalent loads on all data bits and BUSY pins.5元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003TIMING CHARACTERISTICSAll specifications typical at –40°C to 85°C, +VA = 5 V, +VBD = 3 V (see Notes 1, 2, and 3)PARAMETERtCONVtACQtpd1tpd2tw1tsu1tw2tw3tw4th1td1tsu2tw5tentd2td3tw6th2tpd4tsu3th3tdisConversion timeAcquisition timeCONVST low to conversion started (BUSY high)Propagation delay time, end of conversion to BUSY lowPulse duration, CONVST lowSetup time, CS low to CONVST lowPulse duration, CONVST highCONVST falling edge jitterPulse duration, BUSY signal lowPulse duration, BUSY signal highHold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or BUS16/16 input changes) after CONVST lowDelay time, CS low to RD lowSetup time, RD high to CS highPulse duration, RD lowEnable time, RD low (or CS low for read cycle) to data validDelay time, data hold from RD highDelay time, BUS16/16 or BYTE rising edge or falling edge to data validPulse duration, RD high timeHold time, last RD (or CS for read cycle ) rising edge to CONVST falling edgePropagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edgeSetup time, BYTE rising edge to RD falling edgeHold time, BYTE falling edge to RD falling edgeDisable time, RD High (CS high for read cycle) to 3-stated data bus022050Max(td5)003003040005030Min(tACQ)63020020101504020MINTYP600MAX610UNITnsnsnsnsnsnsnspsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnstd5Delay time, BUSY low to MSB data valid delay time(1)All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.(2)See timing diagrams.(3)All timings are measured with 10 pF equivalent loads on all data bits and BUSY pins.6元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003PIN ASSIGNMENTSPFB PACKAGE(TOP VIEW)+VBDRESETBYTECONVSTRDCS+VAAGNDAGND+VAREFMREFMBUSYBDGND+VBDDB0DB1DB2DB3DB4DB5DB6DB7BDGND36353433323130292827262537383940414243444748123456782423222120191817161514139101112+VBDDB8DB9DB10DB11DB12DB13DB14DB15AGNDAGND+VAREFINREFOUTNC+VAAGND+IN–INAGND+VA+VANC – No connectionAGNDAGND7元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003TERMINAL FUNCTIONSNAMEAGNDBDGNDBUSYBYTENO.5, 8, 11, 12,14, 15, 44, 4525, 353639I/O––OIAnalog groundDigital ground for bus interface digital supplyStatus output. High when a conversion is in progress.Byte select input. Used for 8-bit bus reading.0: No fold back1: Low byte D[7:0] of the 16 most significant bits is folded back to high byte of the 16 most significantpins DB[15:8].Convert startChip select8-Bit BusBYTE = 016171819202122232627282930313233763147, 48238414, 9, 10, 13,43, 4624, 34, 37OOOOOOOOOOOOOOOOII–IIOII––D15 (MSB)D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0 (LSB)Inverting input channelNon inverting input channelNo connectionReference inputReference groundReference output. Add 1 µF capacitor between the REFOUT pin and REFM pin when internal referenceis used.Current conversion is aborted and output latches are cleared (set to zeros) when this pin is asserted low.RESET works independantly of CS.Synchronization pulse for the parallel output.Analog power supplies, 5-V dcDigital power supply for busD7D6D5D4D3D2D1D0 (LSB)All onesAll onesAll onesAll onesAll onesAll onesAll onesAll onesBYTE = 1D15 (MSB)D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0 (LSB)16-Bit BusBYTE = 0DESCRIPTIONCONVSTCSDtBData BusDB15DB14DB13DB12DB11DB10DB9DB8DB7DB6DB5DB4DB3DB2DB1DB0–IN+INNCREFINREFMREFOUTRESETRD+VA+VBD4042II8元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003TIMING DIAGRAMStw1CONVSTtpd1BUSYtsu1CSCONVERT†t(CONV)SAMPLING†(When CS Toggle)t(ACQ)BYTEth1tpd4RDtd1tsu2th2t(CONV)tpd2tw3tw2tw4tenDB[15:8]Hi–ZD [15:8]DB[7:0]†Signal internal to deviceHi–ZD [7:0]D [7:0]tdisHi–ZHi–ZFigure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling9元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003tw1CONVSTtpd1BUSYtsu1CSCONVERT†t(CONV)SAMPLING†(When CS Toggle)tpd2tw2tw4tw3t(CONV)t(ACQ)BYTEth1tpd4RD = 0DB[15:8]Hi–ZtenD [15:8]th2tdisD [7:0]Hi–ZDB[7:0]†Signal internal to deviceHi–ZD [7:0]Hi–ZFigure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND10元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003tw1CONVSTtpd1BUSYtpd2tw2tw4tw3CS = 0CONVERT†t(CONV)t(CONV)SAMPLING†(When CS = 0)t(ACQ)BYTEth1tpd4RDtenDB[15:8]Hi–ZD [15:8]D [7:0]tdisHi–Zth2DB[7:0]†Signal internal to deviceHi–ZD [7:0]Hi–ZFigure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling11元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003tw1CONVSTtpd1BUSYtw4tpd2tw2tw3CS = 0CONVERT†t(CONV)t(CONV)SAMPLING†(When CS = 0)t(ACQ)BYTEth1th1td3D [7:0]D [15:8]Next D [15:8]RD = 0tdistd5DB[15:8]Previous D [7:0]DB[7:0]D [7:0]Next D [7:0]†Signal internal to deviceFigure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND—Auto ReadCSRDBYTEtentenDB[15:0]Hi–ZValidtdisHi–ZValidValidtd3tdisHi–ZFigure 5. Detailed Timing for Read Cycles12元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003TYPICAL CHARACTERISTICS†HISTOGRAM (DC Code Spread)NEAR POSITIVE FULL SCALE196608 CONVERSIONS120000+VA = 5 V,Code = 6138390.9SIGNAL-TO-NOISE RATIOvsFREE-AIR TEMPERATUREfi = 50 kHz(+IN– –IN) = Full ScaleSNR – Signal-To- Noise Ratio – dB90.81000008000090.76000090.000090.52000090.4061380613836138590.3–40–25–10520355065TA – Free-Air Temperature – °C80Figure 6Figure 7SIGNAL-TO-NOISE PLUS DISTORTIONvsFREE-AIR TEMPERATURE90.4SINAD – Signal-To-Noise Plus Distortion – dBSFDR – Spurious Free-Dynamic Range – dB90.290.8.6.4.2–40fi = 50 kHz(+IN– –IN) = Full Scale1021011009997969594–40SPURIOUS FREE-DYNAMIC RANGEvsFREE-AIR TEMPERATUREfi = 50 kHz(+IN– –IN) = Full Scale–25–10520355065TA – Free-Air Temperature – °C80–20020406080TA – Free-Air Temperature – °CFigure 8Figure 9†At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted)13元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003TOTAL HARMONIC DISTORTIONvsFREE-AIR TEMPERATURE–94THD – Total Harmonic Distortion – dB–95SNR – Signal-To- Noise Ratio – dB–96–97–98–99–100–101–102–40–25–10fi = 50 kHz(+IN– –IN) = Full Scale520355065809291.1.691.491.29190.0.690.490.290.80SIGNAL-TO-NOISE RATIOvsINPUT FREQUENCYTA = 25°C(+IN– –IN) = Full Scale20406080100TA – Free-Air Temperature – °Cfi – Input Frequency – kHzFigure 10Figure 11SIGNAL-TO-NOISE PLUS DISTORTIONvsINPUT FREQUENCY91.5SINAD – Signal-To-Noise Plus Distortion – dBTA = 25°C(+IN– –IN) = Full Scale14.914.8514.814.75ENOB – Bit14.714.6514.614.5514.514.4588.514.4020406080fi – Input Frequency – kHz100020ENOBvsINPUT FREQUENCYVref = 4.096 V9190.590.06080100fi – Input Frequency – kHzFigure 12Figure 13†At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted)14元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003SPURIOUS FREE-DYNAMIC RANGEvsINPUT FREQUENCY101SFDR – Spurious Free-Dynamic Range – dBTHD – Total Harmonic Distortion – dB1009997969594020406080fi – Input Frequency – kHz100TA = 25°C(+IN– –IN) = Full Scale–94–95–96–97–98–99–100–101TOTAL HARMONIC DISTORTIONvsINPUT FREQUENCYTA = 25°C(+IN– –IN) = Full Scale020406080fi – Input Frequency – kHz100Figure 14Figure 15SUPPLY CURRENTvsSAMPLE RATE3231.5ICC– Supply Current – mA31EG– Gain Error – %FS30.53029.52928.528250TA = 25°CCurrent of +VA only0.00730.00610.00480.00360.00240.00120–0.0012–0.00244.75GAIN ERRORvsSUPPLY VOLTAGETA = 25°CExternal Reference = 4.096 V (REFIN)5007501000Sample Rate – KSPS12505+VA – Supply Voltage – V5.25Figure 16Figure 17†At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted)15元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003OFFSET ERRORvsSUPPLY VOLTAGE0.2.0980.2EO– Offset Error – mVVref– Internal Reference Voltage – VINTERNAL REFERENCE VOLTAGEvsFREE-AIR TEMPERATURE4.0960.1.0940.1TA = 25°CExternal Reference = 4.096 V (REFIN)0.0.0924.09004.755+VA – Supply Voltage – V5.2.088–40–25–1052035506580TA – Free-Air Temperature – °CFigure 18Figure 19GAIN ERRORvsFREE-AIR TEMPERATURE0.0180.60.40.0120.2EG– Gain Error – %FSEO– Offset Error – mV0–0.2–0.4–0.6–0.8OFFSET ERRORvsFREE-AIR TEMPERATURE0.0060–0.006External Reference = 4.096 V (REFIN)–0.012–40–25520355065TA – Free-Air Temperature – °C–1080External Reference = 4.096 V (REFIN)–1–40–25–10520355065TA – Free-Air Temperature – °C80Figure 20Figure 21†At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted)16元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003SUPPLY CURRENTvsFREE-AIR TEMPERATURE30.7530.70ICC– Supply Current – mA30.6530.6030.5530.5030.4530.4030.3530.30–40External Reference = 4.096 V (REFIN)Current of +VA only–25–1052035506580DNL – Differential Nonlinearity (Max) – LSB1.41.210.80.60.4DIFFERENTIAL NONLINEARITY (MAX)vsFREE-AIR TEMPERATUREExternal Reference = 4.096 V (REFIN)0.20–40–25TA – Free-Air Temperature – °C–10520355065TA – Free-Air Temperature – °C80Figure 22Figure 23DIFFERENTIAL NONLINEARITY (MIN)vsFREE-AIR TEMPERATURE–0.68DNL – Differential Nonlinearity (MIN) – LSB–0.69–0.70–0.71–0.72–0.73–0.74–0.75–0.76–0.77–0.78–40–25–10520355065TA – Free-Air Temperature – °C800–403External Reference = 4.096 V (REFIN)INL – Integral Nonlinearity (MAX) – LSB2.5INTEGRAL NONLINEARITY (MAX)vsFREE-AIR TEMPERATURE21.51External Reference = 4.096 V (REFIN)0.5–25–10520355065TA – Free-Air Temperature – °C80Figure 24Figure 25†At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted)17元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003INTEGRAL NONLINEARITY (MIN)vsFREE-AIR TEMPERATURE0INL – Integral Nonlinearity (MIN) – LSB External Reference = 4.096 V (REFIN)–0.5INL – Integral Nonlinearity – LSB3.02.52.01.51.00.50.0–0.5–1.0–1.5–2.0–2.5–40–2.52.0INTEGRAL NONLINEARITYvsREFERENCE VOLTAGEMax–1+VA = +VBD = 5 V,TA = 25°C–1.5Min–2–25–10520355065TA – Free-Air Temperature – °C802.53.03..04.5Vref – Reference Voltage – VFigure 26Figure 27DIFFERENTIAL NONLINEARITYvsREFERENCE VOLTAGE3.53.0DNL – Differential Nonlinearity – LSB2.52.0Max1.51.00.50.0Min–0.5–1.02.0+VA = +VBD = 5 V,TA = 25°C2.53.03..0Vref – Reference Voltage – V4.5Figure 28†At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted)18元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003DNL2.521.510.50–0.5–1–1.5–2–2.5DNL – LSB01638432768Code4915265536TA = 25°C, External Reference = 4.096 V (REFIN)Figure 29INL32INL – LSB1–0–1–2–3–4–501638432768Code4915265536TA = 25°C, External Reference = 4.096 V (REFIN)Figure 30FFT SPECTRUM RESPONSE0Magnitude – dB of Full Scale–20–40–60–80–100–120–140–160–180–2000100200300Frequency – kHz40050060032768 Points, fS = 1.25 MHz,Internal Reference = 4.096 V (REFIN),TA = 25°C, fi = 100 kHz, (+IN– –IN) = Full ScaleFigure 31†At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted)19元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003APPLICATION INFORMATIONMICROCONTROLLER INTERFACINGADS8402 to 8-Bit Microcontroller InterfaceFigure 32 shows a parallel interface between the ADS8402 and a typical microcontroller using the 8-bit data bus.The BUSY signal is used as a falling-edge interrupt to the microcontroller.Analog 5 V0.1 µFAGND10 µFExt Ref Input1 µF0.1 µFAnalog InputREFMAGND+IN–INMicroController+VAREFINDigital 3 VGPIOGPIOP[7:0]RDGPIOINTCSBYTEDB[15:8]RDCONVSTBUSYADS8402BDGNDBDGND+VBD0.1 µFFigure 32. ADS8402 Application Circuitry (using external reference)Analog 5 V0.1 µF10 µFAGND0.1 µF1 µFREFOUTREFM+VAREFINAGNDAGNDADS8402Figure 33. Use Internal Reference20元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003PRINCIPLES OF OPERATIONThe ADS8402 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). Thearchitecture is based on charge redistribution, which inherently includes a sample/hold function. See Figure 32 forthe application circuit for the ADS8402.The conversion clock is generated internally. The conversion time of 610 ns is capable of sustaining a 1.25-MHzthroughput.The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input onthese pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnectedfrom any internal function.REFERENCEThe ADS8402 can operate with an external reference with a range from 2.5 V to 4.2 V. A 4.096-V internal referenceis included. When internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with an 0.1 µFdecoupling capacitor and 1 µF storage capacitor between pin 2 (REFOUT) and pins 47 and 48 (REFM) (seeFigure 33). The internal reference of the converter is double buffered. If an external reference is used, the secondbuffer provides isolation between the external reference and the CDAC. This buffer is also used to recharge all ofthe capacitors of the CDAC during conversion. Pin 2 (REFOUT) can be left unconnected (floating) if externalreference is used.ANALOG INPUTWhen the converter enters the hold mode, the voltage difference between the +IN and –IN inputs is captured on theinternal capacitor array. Both +IN and –IN input has a range of –0.2 V to Vref + 0.2 V. The input span(+IN – (–IN)) is limited to –Vref to Vref.The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and sourceimpedance. Essentially, the current into the ADS8402 charges the internal capacitor array during the sample period.After this capacitance has been fully charged, there is no further input current. The source of the analog input voltagemust be able to charge the input capacitance (25 pF) to an 16-bit settling level within the acquisition time (150 ns)of the device. When the converter goes into the hold mode, the input impedance is greater than 1 GΩ.Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +INand –IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, theconverter’s linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filtersshould be used.Care should be taken to ensure that the output impedance of the sources driving +IN and –IN inputs are matched.If this is not observed, the two inputs could have different setting time. This may result in offset error, gain error andlinearity error which varies with temperature and input voltage.A typical input circuit using TI’s THS4503 is shown in Figure 34. Input from a single-ended source may be convertedinto differential signal for ADS8402 as shown in the figure. In case the source itself is differential then THS4503 maybe used in differential input and differential output mode.21元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 200368 pFRSRGRT1 kΩVCC++_THS450350 Ω20 pFIN–ADS8402IN+OCM+__+VCC–1 kΩ1 kΩ50 Ω68 pFRG, RS, and RT should be chosen such thatRG + RS || RT = 1 k ΩVOCM = 2 V, +VCC = 7 V, and –VCC = –7 VFigure 34. Using THS4503 With ADS8402DIGITAL INTERFACETiming and ControlSee the timing diagrams in the specifications section for detailed information on timing signals and their requirements.The ADS8402 uses an internal oscillator generated clock which controls the conversion rate and in turn thethroughput of the converter. No external clock input is required.Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimumrequirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8402 switches from thesample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signalis important to the performance of the converter. The BUSY output is brought high after CONVST goes low. BUSYstays high throughout the conversion process and returns low when the conversion has ended.Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS whenBUSY is low.Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVSTgoes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output buswith the conversion.Reading DataThe ADS8402 outputs full parallel data in two’s complement format as shown in Table 1. The parallel output is activewhen CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST. Thisis 100 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should be attemptedwithin this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used for multiwordread operations. BYTE is used whenever lower bits of the conversion result are output on the higher byte of the bus.Refer to Table 1 for ideal output codes.22元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003Table 1. Ideal Input Voltages and Output CodesDESCRIPTIONFULL SCALE RANGELeast significant bit (LSB)Full scaleMidscaleZeroANALOG VALUE2Vref2Vref/65536Vref0–VrefDIGITALOUTPUTTWOSCOMPLEMENTDIGITAL OUTPUT TWOS COMPLEMENTBINARY CODE0111 1111 1111 11110000 0000 0000 00001000 0000 0000 0000HEX CODE7FFF00008000The output data is a full 16-bit word (D15–D0) on DB15–DB0 pins (MSB–LSB) if BYTE is low.The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15–DB8. In this casetwo reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on pinsDB15–DB8, then bringing BYTE high. When BYTE is high, the low bits (D7–D0) appears on pins DB15–D8.These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity.BYTEHighLowDATA READ OUTDB15–DB8D7–D0D15–D8DB7–DB0All one’sD7–D0RESETRESET is an asynchronous active low input signal (that works independantly of CS). Minimum RESET low time is20 ns. Current conversion will be aborted no later than 50 ns after the converter is in the reset mode. In addition, alloutput latches are cleared (set to zero’s) after RESET. The converter goes back to normal operation mode no laterthan 20 ns after RESET input is brought high.The converter starts the first sampling period 20 ns after the rising edge of RESET. Any sampling period except forthe one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling edgeof CS, whichever is later.POWER-ON INITIALIZATIONOne RESET pulse followed by three conversion cycles must be given to the converter after powerup to ensure properoperation. The next pulse can be issued once both +VA and +VBD reach 95% of the minimum required value.LAYOUTFor optimum performance, care should be taken with the physical layout of the ADS8402 circuitry.As the ADS8402 offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers,microprocessors, and digital signal processors. The more digital logic present in the design and the higher theswitching speed, the more difficult it is to achieve good performance from the converter.The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, groundconnections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving anysingle conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltagescan affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic,or high power devices.The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the externalevent.On average, the ADS8402 draws very little current from an external reference, as the reference voltage is internallybuffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypasscapacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and 1-µF storage capacitor are recommendedfrom pin 1 (REFIN) directly to pin 48 (REFM). REFM and AGND should be shorted on the same ground plane underthe device.23元器件交易网www.cecb2b.comADS8402www.ti.comSLAS1B – DECEMBER 2002 – REVISED MAY 2003The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analogground. Avoid connections which are close to the grounding point of a microcontroller or digital signal processor. Ifrequired, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists ofan analog ground plane dedicated to the converter and associated analog circuitry.As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate fromthe connection for digital logic until they are connected at the power entry point. Power to the ADS8402 should beclean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible.See Table 2 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is recommended. In somesituations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made upof inductors and capacitors—all designed to essentially low-pass filter the 5-V supply, removing the high frequencynoise.Table 2. Power Supply Decoupling Capacitor PlacementPOWER SUPPLY PLANESUPPLY PINSPin pairs that require shortest path to decoupling capacitorsPins that require no decouplingCONVERTERANALOGSIDECONVERTER ANALOG SIDE(4,5), (8,9), (10,11), (13,15),(43,44), (45,46)12, 14CONVERTERDIGITALSIDECONVERTER DIGITAL SIDE(24,25), (34, 35)3724元器件交易网www.cecb2b.com
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