Robust delay estimation architecture

专利名称：Robust delay estimation architecture发明人：Andres Reial申请号：US10246873申请日：20020918公开号：US07142586B2公开日：20061128

专利附图：

摘要：In a robust delay estimator system and method, an average PDP buffer servesas a source of reliable control information to other stages of the delay estimator. ThePDP output from every path searcher and tuning finger pass is accumulated in theaverage PDP buffer, which maintains average PDP estimates for the whole allowable

delay spread range. The current (i.e., instantaneous) PDP estimate is then added to theaverage PDP using an exponential averaging method. The average PDP buffer stores thecurrent PDP estimate and the average PDP estimate, as well as timing and other types ofinformation regarding the estimates. The information in the average PDP provides thenecessary information for, and is used to control the operation of, all the individual sub-stages of the delay estimation process.

申请人：Andres Reial

地址：Lund SE

国籍：SE

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